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this is information on a product in full production. october 2012 doc id 13317 rev 8 1/42 1 rhf1401 rad-hard 14-bit 30 msps a/d converter datasheet ? production data features qml-v qualified, smd 5962-06260 rad hard: 300 krad(si) tid failure immune (sefi) and latch-up immune (sel) up to 120 mev-cm 2 /mg at 2.7 v and 125 c hermetic package tested at f s = 20 msps low power: 85 mw at 20 msps optimized for 2 vpp differential input high linearity and dynamic performances 2.5 v/3.3 v compatible digital i/o internal reference voltage with external reference option applications digital communication satellites space data acquisition systems aerospace instrumentation nuclear and high-energy physics description the rhf1401 is a 14-bit analog-to-digital converter that uses pure (eldrs-free) cmos 0.25 m technology combining high performance, radiation robustness and very low power consumption. the rhf1401 is based on a pipeline structure and digital error correction to provide excellent static linearity. specifically designed to optimize power consumption, the device only dissipates 85 mw at 20 msps, while maintaining a high level of performance. the device also integrates a proprietary track-and-hold structure to ensure a large effective resolution bandwidth. voltage references are integrated in the circuit to simplify the design and minimize external components. a tri-state ca pability is available on the outputs to allow common bus sharing. a data- ready signal, which is raised when the data is valid on the output, can be used for synchronization purposes. the rhf1401 has an operating temperature range of -55 c to +125 c and is available in a small 48-pin ceramic so-48 package. ceramic so-48 package the upper metallic lid is not electrically connected to any pins, nor to the ic die inside the package. table 1. device summary order code smd pin quality level package lead finish mass eppl (1) temp range rhf1401kso1 - engineering model so-48 gold 1.1 g yes -55 c to +125 c rhf1401kso-01v 5962f0626001vxc qmlv-flight 1. eppl = esa preferred part list www.st.com
contents rhf1401 2/42 doc id 13317 rev 8 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . 12 2.2 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 electrical characteristics (after 300 krad) . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4 results for differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 results for single ended input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 user manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 optimizing the power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 driving the analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.1 differential mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.2 single-ended mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3 reference connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3.1 internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3.2 external voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5.1 digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5.2 digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5.3 digital output load considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.6 pcb layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 definitions of s pecified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1 static parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2 dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
rhf1401 contents doc id 13317 rev 8 3/42 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
list of tables rhf1401 4/42 doc id 13317 rev 8 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. external reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. static accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 10. digital inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 11. dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 12. differential mode output codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 13. single-ended mode output codes with vinb = incm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 14. rhf1401 operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 15. ceramic so-48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 16. order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 17. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
rhf1401 list of figures doc id 13317 rev 8 5/42 list of figures figure 1. rhf1401 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. output buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. data format input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. reference mode control input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 8. output enable input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 9. vrefp and incm input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 10. vrefm input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 11. timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 12. differential configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 13. enob vs. input frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14. sinad vs. input frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 15. thd vs. input frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 16. snr vs. input frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 17. sfdr vs. input frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 18. consumption vs. input frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 19. enob vs. sampling frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 20. sinad vs. sampling frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 21. thd vs. sampling frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 22. snr vs. sampling frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 23. sfdr vs. sampling frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 24. power consumption vs. sampling frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 25. enob vs. vrefp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 26. sinad vs. vrefp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 27. snr vs. vrefp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 28. thd vs. vrefp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 29. enob vs. sine clock, diff. input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 30. clock threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 31. enob vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 32. power consumption vs. temp.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 33. dnl, differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 34. inl, differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 35. single-ended input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 36. enob vs. fin, single-ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 37. sinad vs. fin, single-ended. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 38. thd vs. fin, single-ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 39. snr vs. fin, single-ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 40. sfdr vs. fin, single-ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 41. power consumption vs. fin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 42. enob vs. vin, fin 1 khz, vrefp = 0.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 43. enob vs vin, fin = 2 mhz, vrefp = 0.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 44. enob vs. vin, fin 1 khz, vrefp = 1.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 45. enob vs vin, fin = 2 mhz, vrefp = 1.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 46. enob vs. vin, fin 1 khz, vrefp = 1.2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 47. enob vs vin, fin = 2 mhz, vrefp = 1.2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 48. enob vs. vin, fin 1 khz, vrefp = 1.4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
list of figures rhf1401 6/42 doc id 13317 rev 8 figure 49. enob vs vin, fin = 2 mhz, vrefp = 1.4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 50. rpol values vs. f s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 51. power consumption values vs. f s with internal references disabled . . . . . . . . . . . . . . . . . 26 figure 52. equivalent vin - vinb (differential input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 53. 2 v pp differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 54. differential implementation using a balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 55. optimized single-ended configuration (dc coupling), external refp . . . . . . . . . . . . . . . . 29 figure 56. ac-coupling single-ended input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 57. ac-coupling single-ended input configuration for low frequencies . . . . . . . . . . . . . . . . . . . 30 figure 58. internal voltage reference setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 59. external voltage reference setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 60. example with zeners. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 61. clock input schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 62. output buffer fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 63. output buffer rise time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 64. ceramic so-48 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
rhf1401 description doc id 13317 rev 8 7/42 1 description 1.1 block diagram figure 1. rhf1401 block diagram am04556 vin incm vinb clk gnd or d13 d0 dr oeb dfsb vrefm ipol gnda vrefp stage 1 stage 2 stage n digital data correction buffers internal vrefp sequencer-phase shifting timing vccbi vccbe refmode internal incm biasing current setup
description rhf1401 8/42 doc id 13317 rev 8 1.2 pin connections figure 2. pin connections (top view) gndbi gndbe vccbe nc nc or (msb)d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 (lsb)d0 dr vccbe gndbe vccbi 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 dgnd dgnd clk dgnd dvcc dvcc avcc avcc agnd incm agnd vinb agnd vin agnd vrefm vrefp ipol agnd avcc avcc dfsb oeb refmode
rhf1401 description doc id 13317 rev 8 9/42 1.3 pin descriptions table 2. pin descriptions pin name description observations pin name description observations 1 gndbi digital buffer ground 0 v 25 refmode ref. mode control input 2.5 v/3.3 v cmos input 2 gndbe digital buffer ground 0 v 26 oeb output enable input 2.5 v/3.3 v cmos input 3vccbe digital buffer power supply 2.5 v/3.3 v 27 dfsb data format select input 2.5 v/3.3 v cmos input 4nc not connected to the dice 28 avcc analog power supply 2.5 v 5nc not connected to the dice 29 avcc analog power supply 2.5 v 6 or out of range output cmos output (2.5 v/3.3 v) 30 agnd analog ground 0 v 7 d13(msb) most significant bit output cmos output (2.5 v/3.3 v) 31 ipol analog bias current input 8 d12 digital output cmos output (2.5 v/3.3 v) 32 vrefp top voltage reference can be external or internal 9 d11 digital output cmos output (2.5 v/3.3 v) 33 vrefm bottom voltage reference 0 v 10 d10 digital output cmos output (2.5 v/3.3 v) 34 agnd analog ground 0 v 11 d9 digital output cmos output (2.5 v/3.3 v) 35 vin analog input 1 v pp 12 d8 digital output cmos output (2.5 v/3.3 v) 36 agnd analog ground 0 v 13 d7 digital output cmos output (2.5 v/3.3 v) 37 vinb inverted analog input 1 v pp 14 d6 digital output cmos output (2.5 v/3.3 v) 38 agnd analog ground 0 v 15 d5 digital output cmos output (2.5 v/3.3 v) 39 incm input common mode can be external or internal 16 d4 digital output cmos output (2.5 v/3.3 v) 40 agnd analog ground 0 v 17 d3 digital output cmos output (2.5v /3.3 v) 41 avcc analog power supply 2.5 v 18 d2 digital output cmos output (2.5 v/3.3 v) 42 avcc analog power supply 2.5 v 19 d1 digital output cmos output (2.5 v/3.3 v) 43 dvcc digital power supply 2.5 v 20 d0(lsb) digital output lsb cmos output (2.5 v/3.3 v) 44 dvcc digital power supply 2.5 v 21 dr data ready output (1) cmos output (2.5 v/3.3 v) 45 dgnd digital ground 0 v 22 vccbe digital buffer power supply 2.5 v/3.3 v 46 clk clock input 2.5 v compatible cmos input 23 gndbe digital buffer ground 0 v 47 dgnd digital ground 0 v 24 vccbi digital buffer power supply 2.5 v 48 dgnd digital ground 0 v 1. see load considerations in section 2.2: timing characteristics .
description rhf1401 10/42 doc id 13317 rev 8 1.4 equivalent circuits figure 3. analog inputs figure 4. output buffers am04557 vin or vinb (p a d) avcc agnd 7 pf am04558 d0 d13 7 pf (pad) vccbe gndbe gndbe oeb data vccbe figure 5. clock input figure 6. data format input am04559 clk 7 pf (p a d) dvcc dgnd am04560 df s b 7 pf (p a d) vccbe gndbe figure 7. reference mode control input figure 8. output enable input am04561 refmode 7 pf (p a d) vccbe gndbe am04562 oeb 7 pf (p a d) vccbe gndbe
rhf1401 description doc id 13317 rev 8 11/42 figure 9. vrefp and incm input/output figure 10. vrefm input am0456 3 vrefp 7 pf (p a d) avcc agnd incm 7 pf (p a d) avcc agnd refmode refmode am04564 vrefm avcc agnd 7 pf (p a d) high inp u t imped a nce
electrical characteristics rhf1401 12/42 doc id 13317 rev 8 2 electrical characteristics 2.1 absolute maximum rating s and operating conditions table 3. absolute maximum ratings symbol parameter values unit av cc analog supply voltage 3.3 v dv cc digital supply voltage 3.3 v v ccbi digital buffer supply voltage 3.3 v v ccbe digital buffer supply voltage 3.6 v v in v inb analog inputs: bottom limit ? > top limit -0.6 v ? > av cc +0.6 v v v refp v incm external references: bottom limit ? > top limit -0.6 v ? > av cc +0.6 v v i dout digital output current -100 to 100 ma t stg storage temperature -65 to +150 c r thjc thermal resistance j unction to case 22 c/w r thja thermal resistance junction to ambient 125 c/w esd hbm (human body model) (1) 1. human body model: a 100 pf capacit or is charged to the specified voltage, then discharged through a 1.5 k resistor between two pins of the device. this is done for all couples of connected pin combinations while the other pins are floating. 2kv table 4. operating conditions symbol parameter min typ max unit av cc analog supply voltage 2.3 2.5 2.7 v dv cc digital supply voltage 2.3 2.5 2.7 v v ccbi digital internal buffer supply 2.3 2.5 2.7 v v ccbe digital output buffer supply 2.3 2.5 3.4 v v refp forced top voltage reference 0.7 1 1.4 v v refm bottom external reference voltage 0 0 0.5 v v incm forced common mode voltage 0.2 0.5 1.1 v v in or v inb max. voltage versus gnd 1 1.6 (1) 1. see figure 25. for differential input and figure 42. to figure 49. for single-ended. v min. voltage versus gnd -0.2 gnd v dfsb digital inputs 0 v ccbe v refmode oeb
rhf1401 electrical characteristics doc id 13317 rev 8 13/42 2.2 timing characteristics figure 11. timing diagram the input signal is sampled on the rising edge of the clock while the digital outputs are synchronized on the falling edge of the clock. the duty cyc les on dr and clk are the same. the rising and falling edges of the or pin are synchronized with the falling edge of the dr pin. table 5. timing characteristics symbol parameter test co nditions min typ max unit dc clock duty cycle f s = 20 msps 45 50 65 % t od data output delay (fall of clock to data valid) (1) 1. as per figure 11 . 10 pf load capacitance 5 7.5 13 ns t pd data pipeline delay (2) 2. if the duty cycle does not equal 50%: t pd = 7 cycles + clk pulse width. duty cycle = 50% 7.5 7.5 7.5 cycles t on falling edge of oeb to digital output valid data 1ns t off rising edge of oeb to digital output tri-state 1ns t rd data rising time 10 pf load capacitance 6 ns t fd data falling time 10 pf load capacitance 3 ns n- 2 n-1 n n+1 n+2 n+ 3 n+4 n+5 n+6 n+7 n+ 8 n- 8 n-7 n-6 n n-5 n -4 n+1 n- 3 n-1 hz s t a te an a log inp u t clk oeb d a t a o u tp u t dr toff ton tpd + tod tod am06120 or tod
electrical characteristics rhf1401 14/42 doc id 13317 rev 8 2.3 electrical characte ristics (after 300 krad) unless otherwise specified, the test conditions in the following tables are: avcc = dvcc = vccbi =vccbe = 2.5 v, f s =20 msps, f in = 15 mhz, v in at -1 dbfs, vrefp = 1 v, incm = 0.5 v, vrefm = 0 v, t amb = 25 c. table 6. analog inputs symbol parameter test conditions min typ max unit v in -v inb full-scale reference voltage (fs) (1) 1. see section 4: definitions of specified parameters for more information. vrefp = 1 v (forced) vrefm = 0 v 2v pp c in input capacitance 7 pf z in input impedance f s = 20 msps 3.3 k erb effective resolution bandwidth (1) 70 mhz table 7. internal reference voltage symbol parameter test co nditions min typ max unit r out output resistance of internal reference refmode = 0 internal reference on 30 refmode = 1 internal reference off 7.5 k v refp top internal reference voltage refmode = 0 0.76 0.84 0.95 v v incm input common mode voltage refmode = 0 0.40 0.44 0.50 v table 8. external reference voltage (1) 1. see figure 59 .& figure 60 symbol parameter test co nditions min typ max unit v refp forced top reference voltage refmode = 1 0.7 1.4 v v refm forced bottom ref voltage refmode = 1 0 0.5 v v incm forced common mode voltage refmode = 1 0.2 1.1 v table 9. static accuracy symbol parameter test conditions min typ max unit dnl differential non-linearity (1) 1. see figure 33 and section 4 for more information. this parameter is not tested. f in = 1.5 msps v in at +1 dbfs f s = 1.5 msps 0.4 lsb inl integral non-linearity (2) 2. see figure 34 and section 4 for more information. this parameter is not tested. 3 lsb monotonicity and no missing codes guaranteed
rhf1401 electrical characteristics doc id 13317 rev 8 15/42 higher values of snr, sinad and enob can be obtained by increasing the full-scale range of the analog input if the sampling frequency allows it. table 10. digital inputs and outputs symbol parameter test co nditions min typ max unit clock input ct clock threshold dv cc = 2.5 v 1.25 v ca square clock amplitude (dc component = 1.25 v) dv cc = 2.5 v 0.8 2.5 vpp digital inputs v il logic "0" voltage v ccbe = 2.5 v 0 0.25 x v ccbe v v ih logic "1" voltage v ccbe = 2.5 v 0.75 x v ccbe v ccbe v digital outputs v ol logic "0" voltage i ol = -10 a 0 0.25 v v oh logic "1" voltage i oh = 10 a v ccbe -0.25 v i oz high impedance leakage current oeb set to v ih -15 15 a c l output load capacitance high clk frequencies 15 pf table 11. dynamic characteristics symbol parameter test conditions min typ max unit sfdr spurious free dynamic range f in = 15 mhz f s = 20 msps v in at -1 dbfs internal references c l = 6 pf 70 91 dbfs snr signal to noise ratio 66 70 db thd total harmonic distortion 70 86 db sinad signal to noise and distortion ratio 65 70 db enob effective number of bits 10.6 11.5 bits
electrical characteristics rhf1401 16/42 doc id 13317 rev 8 2.4 results for differential input setup avcc = dvcc = vccbi = vccbe = 2.5v vrefp = 1 v vrefm = 0 v incm = vrefp/2 refmode = 1 (internal references are disabled) vin = full scale - 0.3 db ta m b = 2 5 c a square clock is applied unless other test conditions are specified. figure 12. differential configuration c f is a filter capacitor to cut th e hf noise. its value is 10 nf for input frequencies equal to or below 20 khz. the value of the capacitor is divided by two when the input frequency is multiplied by 2. am04565 differential input signal vin vinb incm refm refp ground external 1v external 2.5 v vccbe vccbi avcc dvcc vocm generator v oc m g enerat o r c f
rhf1401 electrical characteristics doc id 13317 rev 8 17/42 figure 13. enob vs. input frequency figure 14. sinad vs. input frequency 10.8 11.2 11.6 12 enob (bits) fs = 10 ksps 100 ksps 1 msps 10 10.4 10e +0 100e +0 1e +3 10e +3 100e +3 1e +6 10e +6 100e +6 input frequency 10 msps 30 msps -70 -68 -66 -64 -62 -60 s inad (db ) fs = 10 ksps 100 ksps 1 msps 10 msps 30 msps -76 -74 -72 1e +1 1e +2 1e +3 1e +4 1e +5 1e +6 1e +7 1e +8 input frequency figure 15. thd vs. input frequency figure 16. snr vs. input frequency -80 -75 -70 -65 -60 thd (db) fs = 10 ksps 100 ksps 1 msps 10 msps 30 msps -90 -85 1e +1 1e +2 1e +3 1e +4 1e +5 1e +6 1e +7 1e +8 input frequency 66 68 70 72 74 76 snr (db) fs = 10 ksps 100 ksps 1m 60 62 64 1e +1 1e +2 1e +3 1e +4 1e +5 1e +6 1e +7 1e +8 input frequency 1 m sps 10 msps 30 msps figure 17. sfdr s. input frequency figure 18. consumption s. input frequency 70 75 80 85 90 sfdr (db) fs = 10 ksps 100 ks ps 1 msps 60 65 1e +1 1e +2 1e +3 1e +4 1e +5 1e +6 1e +7 1e +8 input fr equency 10 msps 30 msps 60 70 80 90 100 110 120 w er cons umption (mw) fs = 10 ksps 100 ksps 1 msps 10 msps 30 msps 30 40 50 1e +1 1e +2 1e +3 1e +4 1e +5 1e +6 1e +7 1e +8 po input frequency
electrical characteristics rhf1401 18/42 doc id 13317 rev 8 figure 19. enob vs. sampling frequency f igure 20. sinad vs. sampling frequency 11 11.5 12 enob (bits) fin = 10 hz 1 khz 50 khz 10 10.5 1e +4 1e +5 1e +6 1e +7 1e +8 s ampling frequency 50 khz 2 mhz 10 mhz -70 -68 -66 -64 -62 -60 sinad (db) fin = 10 hz 1 khz 50 khz 2 mhz 10 mhz -74 -72 1e +4 1e +5 1e +6 1e +7 1e +8 sampling frequency figure 21. thd vs. sampling frequency figure 22. snr vs. sampling frequency -80 -75 -70 -65 -60 thd (db) fin = 10 hz 1 khz 50 khz 2 mhz 10 mhz -90 -85 1e +4 1e +5 1e +6 1e +7 1e +8 s ampling frequency 66 68 70 72 74 76 snr (db) fin = 10 hz 1 khz 50 khz 60 62 64 1e +4 1e +5 1e +6 1e +7 1e +8 s ampling frequency 50 khz 2 mhz 10 mhz figure 23. sfdr s. sampling frequency figure 24. power consumption s. sampling frequency 70 75 80 85 90 sfdr (db) fin = 10 hz 1 khz 50 kh 60 65 1e +4 1e +5 1e +6 1e +7 1e +8 s ampling frequency 50 kh z 2 mhz 10 mhz 80 100 120 140 160 180 o wer consumption (mw) fin = 10 hz 1 khz 50 khz 2 mhz 10 mhz 20 40 60 1e +4 1e +5 1e +6 1e +7 1e +8 p o s ampling frequency
rhf1401 electrical characteristics doc id 13317 rev 8 19/42 figure 25. enob vs. vrefp figure 26. sinad vs. vrefp 10.5 11 11.5 12 12.5 enob (bits) fs = 10 ksps 100 ksps 1msps 9.5 10 0.8 0.9 1 1.1 1.2 1.3 1.4 external vrefp (v) 1 msps 10 msps 20 msps 25 msps 30 msps 35 msps -70 -65 -60 -55 -50 sinad (db) fs = 10 ksps 100 ksps 1 msps 10 msps 20 msps 25 msps 30 msps 35 msps -80 -75 0.8 0.9 1 1.1 1.2 1.3 1.4 e xternal vrefp (v) figure 27. snr vs. vrefp figure 28. thd vs. vrefp 65 70 75 80 snr (db) fs = 10 ksps 100 ksps 1 msps 55 60 0.8 0.9 1 1.1 1.2 1.3 1.4 e xternal vrefp (v) 10 msps 20 msps 25 msps 30 msps 35 msps -75 -70 -65 -60 -55 -50 thd (db) fs = 10 ksps 100 ksps 1 msps 10 msps 20 msps 25 msps 30 msps 35 msps -90 -85 -80 0.8 0.9 1 1.1 1.2 1.3 1.4 e xternal vrefp (v) figure 29. enob vs. sine clock, diff. input figure 30. clock threshold vs. temperature 11 11.5 12 enob (bits) fin = 10 hz 1 khz 50 khz 10 10.5 1 msps 10 msps 100 msps s ampling frequency 2 mhz 10 mhz
electrical characteristics rhf1401 20/42 doc id 13317 rev 8 figure 31. enob vs. temperature figure 32. power consumption vs. temp. 10.5 11 11.5 12 12.5 enob (bits) fs = 200 sps 1 ksps 10 k 9 9.5 10 -55 -35 -15 5 25 45 65 85 105 125 temperature (c) 10 k sps 100 ksps 1 msps 20 30 40 50 e r consumption (mw) r pol=330 kohms fs = 10 ksps 100 k 0 10 -55 -35 -15 5 25 45 65 85 105 125 pow e temperature (c) 100 k sps 1 msps figure 33. dnl differential input figure 34. inl differential input dnl (lsb) inl (lsb)
rhf1401 electrical characteristics doc id 13317 rev 8 21/42 2.5 results for single ended input setup avcc = dvcc = vccbi = vccbe = 2.5 v vrefp = 1 v vrefm = 0 v incm = vin/2 refmode = 1 (internal references are disabled) vin = 1 vpp ta m b = 2 5 c a square clock is applied unless other test conditions are specified. in the following graphs, the input signal is seldom full scale. figure 35. single-ended input configuration c f is a filter capacitor to cut th e hf noise. its value is 10 nf for input frequencies equal to or below 20 khz. the value of the capacitor is divided by two when the input frequency is multiplied by 2. am04566 single ended input signal vin vinb incm refm refp ground external 1v external 2.5 v vccbe vccbi avcc dvcc vocm generator c f v oc m g enerat o r
electrical characteristics rhf1401 22/42 doc id 13317 rev 8 figure 36. enob vs. fin, single-ended f igure 37. sinad vs. fin, single-ended figure 38. thd vs. fin, single-ended f igure 39. snr vs. fin, single-ended figure 40. sfdr vs. fin, single-ended f igure 41. power consumption vs. fin 10 10.5 11 11.5 enob (bits) fs = 10 ksps 100 ksps 9 9.5 1e +1 1e +2 1e +3 1e +4 1e +5 1e +6 1e +7 1e +8 input frequency 100 ksps 1 msps 10 msps 30 msps -60 -55 -50 s inad (db ) fs = 10 ksps 100 ksps 1 msps 10 msps 30 msps -70 -65 1e +1 1e +2 1e +3 1e +4 1e +5 1e +6 1e +7 1e +8 input frequency -75 -70 -65 -60 -55 thd (db) fs = 10 ksps 100 ksps 1 msps 10 msps 30 msps -85 -80 1e +1 1e +2 1e +3 1e +4 1e +5 1e +6 1e +7 1e +8 input frequency 61 64 67 70 snr (db) fs = 10 ksps 100 ksps 55 58 1e +1 1e +2 1e +3 1e +4 1e +5 1e +6 1e +7 1e +8 input frequency 1 msps 10 msps 30 msps 65 70 75 80 85 sfdr (db) fs = 10 ksps 00 k 55 60 1e +1 1e +2 1e +3 1e +4 1e +5 1e +6 1e +7 1e +8 input fr equency 1 00 k sps 1 msps 10 msps 30 msps 60 80 100 120 w er cons umption (mw) fs = 10 ksps 100 ksps 1 msps 10 msps 30 msps 20 40 1e +1 1e +2 1e +3 1e +4 1e +5 1e +6 1e +7 1e +8 po input frequency
rhf1401 electrical characteristics doc id 13317 rev 8 23/42 figure 42. enob vs. vin, fin 1 khz, vrefp = 0.8 v f igure 43. enob vs vin, fin = 2 mhz, vrefp = 0.8 v figure 44. enob vs. vin, fin 1 khz, vrefp = 1.0 v f igure 45. enob vs vin, fin = 2 mhz, vrefp = 1.0 v figure 46. enob vs. vin, fin 1 khz, vrefp = 1.2 v f igure 47. enob vs vin, fin = 2 mhz, vrefp = 1.2 v 10.0 10.5 11.0 11.5 enob (bits) fin = 1 khz - vrefp=0.8v fs = 10 ksps 9.0 9.5 1.01.11.21.31.41.51.6 vin (vpp) 100 ksps 1 msps 10 msps 20 msps 25 msps 30 msps 10.0 10.5 11.0 11.5 enob (bits) fin = 2mhz - vrefp=0.8v fs = 9.0 9.5 1.0 1.1 1.2 1.3 1.4 1.5 1.6 vin (vpp) 2 msps 10 msps 20 msps 25 msps 30 msps 10.0 10.5 11.0 11.5 enob (bits) fin = 1khz - vrefp=1.0v fs = 10 ksps 100 k 9.0 9.5 1.0 1.1 1.2 1.3 1.4 1.5 1.6 vin (vpp) 100 k sps 1 msps 10 msps 20 msps 25 msps 30 msps 10.0 10.5 11.0 11.5 enob (bits) fin = 2mhz - vrefp=1.0v fs = 9.0 9.5 1.01.11.21.31.41.51.6 vin (vpp) 2 msps 10 msps 20 msps 25 msps 30 msps 10.0 10.5 11.0 11.5 enob (bits) fin = 1khz - vrefp=1.2v fs = 10 ksps 9.0 9.5 1.0 1.1 1.2 1.3 1.4 1.5 1.6 vin (vpp) 100 k sps 1 msps 10 msps 20 msps 25 msps 30 msps 10.0 10.5 11.0 11.5 enob (bits) f in = 2mhz - v r e f p =1.2v fs = 9.0 9.5 1.0 1.1 1.2 1.3 1.4 1.5 1.6 vin (vpp) fs = 2 msps 10 msps 20 msps 25 msps 30 msps
electrical characteristics rhf1401 24/42 doc id 13317 rev 8 figure 48. enob vs. vin, fin 1 khz, vrefp = 1.4 v f igure 49. enob vs vin, fin = 2 mhz, vrefp = 1.4 v 10.0 10.5 11.0 11.5 enob (bits) fin = 1khz - vrefp=1.4v fs = 10 ksps 9.0 9.5 1.0 1.1 1.2 1.3 1.4 1.5 1.6 vin (vpp) 100 ksps 1 msps 10 msps 20 msps 25 msps 30 msps 10.0 10.5 11.0 11.5 enob (bits) fin = 2mhz - vrefp=1.4v fs = 9.0 9.5 1.01.11.21.31.41.51.6 v in (v pp) 2 msps 10 msps 20 msps 25 msps 30 msps
rhf1401 user manual doc id 13317 rev 8 25/42 3 user manual 3.1 optimizing the power consumption the polarization current in the input stage is set by an external resistor (r pol ). when selecting the resistor value, it is possible to optimize the power consumption according to the sampling frequency of the application. for this purpose, an external r pol resistor is placed between the ipol pin and the analog ground. the values in figure 50 are achieved with vrefp = 1 v, vrefm = 0 v, incm = 0.5 v and the input signal is 2 vpp with a differential dc connection. if the conditions are changed, the rpol resistor varies slightly. figure 50 shows the optimum rpol resistor value to obtain the best enob value. it also shows the minimum and maximum values to get good results. enob decreases by approximately 0.2 db when you change rpol from optimum to maximum or minimum. if rpol is higher than the maximum value, there is not enough polarization current in the analog stage to obtain good results. if rpol is below the minimum, thd increases significantly. therefore, the total dissipation can be adjuste d across the entire samp ling range to fulfill the requirements of applications where power saving is critical. for sampling frequencies below 2 mhz, the optimum resistor value is approximately 400 kohms. figure 50. rpol values vs. f s the power consumption depends on the rpol value and the sampling frequency. in figure 51 , it is shown with the internal references disabled (refmode = 1) and rpol defined in figure 50 as the optimum. 100 1000 is tor (k ohms ) maximum optimum minimum 1 10 0 5 10 15 20 25 30 35 40 r pol res s ampling frequency (ms ps )
user manual rhf1401 26/42 doc id 13317 rev 8 figure 51. power consumption values vs. f s with internal references disabled 80 100 120 140 160 180 200 o nsumption (mw) 0 20 40 60 0 5 10 15 20 25 30 35 40 power c o s ampling frequency (mhz)
rhf1401 user manual doc id 13317 rev 8 27/42 3.2 driving the analog input the input frequency can range from dc to tens of mhz. the input stages (vin and vinb) have a specia l design that limits the input amplitude. for each of them, the maximum input voltage is about 1.6 v for low sampling frequencies and less for high sampling frequencies. low voltage is ground. consequently, the maximum input voltage read by the adc for single-ended mode is 1.6 v regardless of the vrefp and vrefm voltages. 3.2.1 differential mode the incm value must be equal to the medium input voltage value. in differential mode, high sampling limitation is seen in figure 25. for all input frequencies, it is mandatory to add a capacitor on the pcb (between vin and vinb) to cut the hf noise. the lower the frequency, the higher the capacitor. the full-scale range is twice the difference between vrep and vrefm. figure 52. equivalent vin - vinb (differential input) the rhf1401 is designed to obtain optimum performance when driven on differential inputs with a differential amplitude of two volts peak-to-peak (2 v pp ). this is the result of 1 v pp on the vin and vinb inputs in phase opposition. the rhf1401 is specifically designed to meet sampling requirements for intermediate frequency (if) input signals. in particular, the track-and-hold in the first stage of the pipeline is designed to minimize the linearity limitations as the analog frequency increases. table 12. differential mode output codes vin - vinb = dfsb = 1 dfsb = 0 + (vrefp-vrefm) 3fff 1fff 01fff3fff - (vrefp-vrefm) 0000 2000 am04567 incm (level 0, code 8 191) (level - f s , code 0) (level + f s , code 16 383 ) f s (f u ll- s c a le) = 2(vrefp - vrefm) vin vinb vin -vinb
user manual rhf1401 28/42 doc id 13317 rev 8 figure 53. 2 v pp differential input figure 54 shows a differential input solution. the input signal is fed to the transformer?s primary, while the secondary drives both adc inputs. the transformer must be matched with generator output impedance: 50 in this case for proper matching with a 50 generator. the tracks between the secondary and vin and vinb pins must be as short as possible. figure 54. differential implementation using a balun the input common-mode voltage of the adc (incm) is connected to the center tap of the transformer?s secondary in order to bias the input signal around the common voltage (see ta bl e 7: internal reference voltage ).the incm is decoupled to ma intain a low noise level on this node. ceramic technology for decoupling provides good capacitor stability across a wide bandwidth. am04570 vin vinb 1 vp -p incm 1 vp -p ground refp refm vin -vinb (2 vp-p) 1 v incm incm 0.5v refmode 2.5 v am04571 100 nf* ceramic (as close as possible to incm pin) 50 33 pf adt1 -1 1:1 analog input signal 50 track short track 470 nf* ceramic (as close as possible to the transformer) external incm (optional) *the use of a ceramic technology is preferable for a large bandwidth stability of the capacitor vin vinb incm (50 output)
rhf1401 user manual doc id 13317 rev 8 29/42 3.2.2 single-ended mode figure 55. optimized single-ended configuration (dc coupling), external refp the rhf1401 is designed for use in a differential input configuration. nevertheless, it can achieve good performance in a single-ended input configuration. in single-ended, performances depend on the input voltage, input frequency, voltage of references and sampling frequency (refer to figure 42. to figure 49. ) vrefp and incm internal voltage references are not adapted to single-ended mode. some applications may require a single-ended input, which can easily be achieved with the configuration shown in figure 56 , figure 57 for ac coupling or figure 35. for dc coupling. however, with this type of configuration, a degradation in the rated performance of the rhf1401 may occur compared with a differential configuration. a sufficiently decoupled dc reference should be used to bias the rhf1401 in puts. an ac-coupled analog input can also be used and the dc analog level set with a high value resistor r (6 k to 100 k ) connected to a proper dc source. cin and r behave like a high-pass filter and are calculated to set the lowest possible cut-off frequency. each input is limited to about 1.6 v due to the cmos transistor on the input path. voltage can be a bit more or less than 1.6 v depending on temperature, avcc, and variations from one die to another (see figure 3 for the analog input schematic). this ?input limitation? is independent of the vrefp and vrefm values. table 13. single-ended mode output codes with vinb = incm vin = dfsb = 1 dfsb = 0 incm + (vrefp-vrefm) 3fff 1fff incm 1fff 3fff incm - (vrefp-vrefm) 0000 2000 am04569 vin vinb external vin incm ground incm vin refm max = 1.6v incm 0 v (ground) refp external
user manual rhf1401 30/42 doc id 13317 rev 8 the or pin should rise to 1 when the signal is out of range. however, when vrefp = 0.8 v, vrefm = 0 v, and input voltage max = 1.6 v, the adc may not read the maximum input voltage due to the cmos input transistor. consequently, the or pin does not rise to 1. to avoid this situation occurring, it is recommended to limit the input amplitude to 1.5 v, vrefp to 0.75 v, and vrefm to 0 v. figure 56. ac-coupling single- ended input configuration figure 57. ac-coupling single-ended input configuration for low frequencies the c capacitor is efficient in reducing nois e at high frequencies. when coupled with the resistors, r and c together behave like a high-pass filter. for example, if r = 10 k and c = 33 pf, the cut-off frequency of this filter equals 482 khz. am04572 100 nf cer a mic * ( as clo s e as po ss i b le to incm pin) r cin s hort tr a ck 50 extern a l incm (option a l) r vin vinb incm s hort tr a ck 470 pf cer a mic * 100 nf cer a mic * * the us e of a cer a mic technology i s prefer ab le for a l a rge ba ndwidth s t ab ility of the c a p a citor an a log inp u t s ign a l (50 o u tp u t) 50 tr a ck am0457 3 100 nf cer a mic * ( as clo s e as po ss i b le to incm pin) r s hort tr a ck 50 extern a l incm (option a l) * cer a mic technology for a l a rge ba ndwidth s t ab ility of the c a p a citor r vin vinb incm s hort tr a ck c an a log inp u t s ign a l (50 o u tp u t) 50 tr a ck cin
rhf1401 user manual doc id 13317 rev 8 31/42 3.3 reference connections 3.3.1 internal voltage reference in standard configuration, the adc is biased with two internal voltage references: vrefp and incm. they should be decoupled to minimize low and high frequency noise. when the refmode pin is set to 0 both internal voltage references are enabled and they can drive external components or be forced by an external value. the vrefm pin has no internal reference and must be connected to a voltage reference. it is usually connected to the analog ground. figure 58. internal voltage reference setting 3.3.2 external voltage reference external voltage references can be used for specific applications requiring better linearity, enhanced temperature behavior, or different voltage values (see ta b l e 7: internal reference voltage ). internal voltage references are disabled when the refmode pin is equal to 1. in this case, external voltage references must be applied to the device. external voltage references can be applied when internal voltage references are disabled or not. when internal voltage reference are disabled, adc consumption is about 13 ma less than when they are enabled. the external voltage references with the configuration shown in figure 59 and figure 60 can be used to obtain optimum performance. decoupling is achieved by using ceramic capacitors, which provide optimum linearity versus frequency. am04574 470 nf* 100 nf* vin vinb vrefm vrefp as close as possible to the adc pins *the use of a ceramic technology is preferable for a large bandwidth stability of the capacitor. refmode 470 nf* 100 nf* incm i n c m
user manual rhf1401 32/42 doc id 13317 rev 8 note: *the use of ceramic technology is preferab le to ensure large b andwidth stability of the capacitor. in multi-channel applications, the high impedance input (when refmode = 1) of the references allows one to drive several adcs with only two voltage reference devices. in differential mode the voltage of the analog input common mode (incm) should be around v refp /2. higher levels introduce more distortion. figure 59. external voltage reference setting figure 60. example with zeners am04575 470 nf* 100 nf* vin vinb vrefm vcca vrefp as close as possible to the adc pins dc source incm refmode 470 nf* 100 nf* dc source am04576 470 nf* 100 nf* r as close as possible to the adc pins 470 nf* 100 nf* vin vinb vrefm vcca vrefp r1 as close as possible to the adc pins refmode 470 nf* 100 nf* 470 nf* 100 nf* r2 incm
rhf1401 user manual doc id 13317 rev 8 33/42 3.4 clock input the quality of the converter very much depends on the accuracy of the clock input in terms of jitter. the use of a low-jitter, cryst al-controlled oscilla tor is recommended. the following points should also be considered. the clock?s power supplies must be independent of the adc?s output supplies to avoid digital noise modulation at the output. when powered-on, the circuit needs several clock periods to reach its normal operating conditions. figure 61. clock input schematic the signal applied to the clk pin is critical to obtain full performance from the rhf1401. below 10 mhz, the sine clock does not have transition times fast enough to achieve good performances. it is recommended to use a square signal with fast transition times and to place proper termination resistors as close as possible to the device. the sampling instant is determined by the clock signal?s rising edge. the jitter associated with this instant must be as low as possible to avoid snr degradation on fast moving input signals. to make sure any error is less than 0.5 lsb, the total jitter t j must satisfy the following condition for a full-scale input signal. for example, the total jitter with a 14-bit resolution for a 10 mhz full-scale input should be no more than 1 picosecond (rms). in most cases, the clock signal jitter is responsible for noise. therefore, you must pay attention to the clock signal when fast signals are acquired with a low frequency clock. am04577 50 clk dvcc/2 dvcc/2 square clock sine clock short track clk short track 50 50 clock generator t 1 f in 2 n1 + ?? -------------------------------------- - <
user manual rhf1401 34/42 doc id 13317 rev 8 3.5 operating modes extra functionalities are provided to simplify the application board as much as possible. the operating modes offered by the rhf1401 are described in ta bl e 14 . 3.5.1 digital inputs data format select bit (dfsb): when set to low level (v il ), the digital input dfsb provides a two?s complement digital output msb. this can be of interest when performing some further signal processing. when set to high level (v ih ), dfsb provides standard binary output coding (see ta b l e 12 ). output enable bit (oeb): when set to low level (v il ), all digital outputs remain active. when set to high level (v ih ), all digital output buffers are in a high impedance state while the converter goes on sampling. when oeb is set to a low level again, the data arrives on the output with a very short t on delay. this feature enables the chip select of the device. figure 11: timing diagram summarizes this functionality. reference mode control (refmode): this allows the internal or external settings of the voltage references vrefp and incm. refmode = 0 for internal references, refmode = 1 for external references (and disables both references vrefp and incm). 3.5.2 digital outputs out of range (or): this function is implemented on the output stage in order to set an "out- of-range" flag whenever the digital data is over the full-scale range. typically, there is a detection of all data at ?0? or a ll data at ?1?. it sets an output signal or, which is in a low level state (v ol ) when the data stays within the range, or in a high-level state (v oh ) when the data read by the adc is out of range. data ready (dr): the data ready output is an image of the clock being synchronized on the output data (d0 to d13). this is a very helpful signal that simplifies the synchronization of the measurement equipment of the controlling dsp. like all other digital outputs, dr goes into high impedance when oeb is set to a high level, as shown in figure 11: timing diagram . table 14. rhf1401 operating modes inputs outputs analog input differential amplitude dfsb oeb or dr most significant bit (msb) (v in -v inb ) above maximum range hlhclkd13 l l h clk d13 complemented (v in -v inb ) below minimum range hlhclkd13 l l h clk d13 complemented (v in -v inb ) within range hllclkd13 l l l clk d13 complemented xxhhz (1) 1. high impedance. hz hz (all digital outputs are in high impedance)
rhf1401 user manual doc id 13317 rev 8 35/42 3.5.3 digital output load considerations the features of the internal output buffers limit the maximum load on the digital data output. in particular, the shape and amplitude of the data ready signal, toggling at the clock frequency, can be weakened by a higher equivalent load. in applications that im pose higher load conditions, it is recommended to use the falling edge of the master clock instead of the data ready signal. this is possible because the output transitions are interna lly synchronized with the falling edge of the clock. 3.6 pcb layout precautions the use of dedicated analog and digital ground planes on the pcb is recommended for high-speed circuit applications to provide low parasitic inductance and resistance. agnd is connected to the analog ground plane and dgnd, gndbi, gndbe are connected to the digital ground plane. to minimize the transition current when the output changes, the capacitive load at the digital outputs must be reduced as much as possible by using the shortest-possible routing tracks. one way to reduce the capacitive load is to remove the ground plane under the output digital pins and layers at high sampling frequencies. the separation of the analog signal from the clock signal and digital outputs is mandatory to prevent noise from coupling onto the input signal. power supply bypass capacitors must be placed as close as possible to the ic pins to improve high-frequency bypassing and reduce harmonic distortion. all leads must be as short as possible, especially for the analog input, so as to decrease parasitic capacitance and inductance. choose the smallest-possible component sizes (smd). figure 62. output buffer fall time figure 63. output buffer rise time 10 15 20 25 fall time (ns) vccbe=2.5v vccbe=3.3v 0 5 0 1020304050 load capacitor (pf) 10 15 20 25 rise time (ns) vccbe=2.5v vccbe=3.3v 0 5 0 1020304050 load capacitor (pf)
definitions of specified parameters rhf1401 36/42 doc id 13317 rev 8 4 definitions of specified parameters 4.1 static parameters differential non-linearity (dnl) the average deviation of any output code width from the ideal code width of 1 lsb. integral non-linearity (inl) an ideal converter exhibits a transfer function that is a straight line from the starting code to the ending code. the inl is the deviation from this ideal line for each transition. 4.2 dynamic parameters spurious free dynamic range (sfdr) the ratio between the power of the worst spurious signal (not always a harmonic) and the amplitude of the fundamental tone (signal power) over the full nyquist band. expressed in dbc. total harmonic distortion (thd) the ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. expressed in db. signal to noise ratio (snr) the ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the nyquist band (f s /2) excluding dc, fundamental and the first five harmonics. reported in db. signal-to-noise and distortion ratio (sinad) a similar ratio to the snr but that includes the harmonic distortion components in the noise figure (not the dc signal). expressed in db. from sinad, the effective number of bits (enob) can easily be deduced using the formula: sinad = 6.02 enob + 1.76 db when the analog input signal is not full-scale (fs) but has an a 0 amplitude, the sinad expression becomes: sinad = 6.02 enob + 1.76 db + 20 log (a 0 / fs) analog input bandwidth the maximum analog input frequency at which the spectral response of a full power signal is reduced by 3 db. higher values can be achieved with smaller input levels. pipeline delay the delay between the initial sample of th e analog input and th e availability of the corresponding digital data output on the output bus. also called data latency. expressed as a number of clock cycles.
rhf1401 package information doc id 13317 rev 8 37/42 5 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package information rhf1401 38/42 doc id 13317 rev 8 figure 64. ceramic so-48 package mechanical drawing note: the upper metallic lid is not electrically connected to any pins, nor to the ic die inside the package. connecting unused pins or metal lid to ground or to the power supply will not affect the electrical characteristics. table 15. ceramic so-48 package mechanical data ref. dimensions millimeters inches min. typ. max. min. typ. max. a 2.18 2.47 2.72 0.086 0.097 0.107 b 0.20 0.254 0.30 0.008 0.010 0.012 c 0.12 0.15 0.18 0.005 0.006 0.007 d 15.57 15.75 15.92 0.613 0.620 0.627 e 9.52 9.65 9.78 0.375 0.380 0.385 e1 10.90 0.429 e2 6.22 6.35 6.48 0.245 0.250 0.255 e3 1.52 1.65 1.78 0.060 0.065 0.070 e 0.635 0.025 f 0.20 0.008 l 12.28 12.58 12.88 0.483 0.495 0.507 p 1.30 1.45 1.60 0.051 0.057 0.063 q 0.66 0.79 0.92 0.026 0.031 0.036 s1 0.25 0.43 0.61 0.010 0.017 0.024
rhf1401 ordering information doc id 13317 rev 8 39/42 6 ordering information table 16. order codes note: contact your local st sales office for info rmation regarding the sp ecific conditions for products in die form and qml-q versions. order code quality level temp range package marking packing rhf1401kso1 engineering model -55 c to +125 c so-48 rhf1401kso1 strip pack rhf1401kso-01v qmlv-flight 5962f0626001vxc
revision history rhf1401 40/42 doc id 13317 rev 8 7 revision history table 17. document revision history date revision changes 29-jun-2007 1 first public release. failure immune and latchup immune value increased to 120 mev-cm2/mg. updated package mechanical information. removed reference to non rad-hard components from external references, common mode: on page 16 . 29-oct-2007 2 updated figure 1: rhf1401 block diagram . added explanation on figure 3: timing diagram . added introduction to section 6: typical performance characteristics . updated section 7.2: clock signal requirements and section 7.3: power consumption optimization. added section 7.4: low sampling rate recommendations. updated information on data ready signal in section 7.5: digital inputs/outputs . added figure 24: impact of clock frequency on rhf1401 performance and figure 25: clk signal derivation . 09-nov-2009 3 changed input clock features in table 10 . modified ta b l e 1 4 . added figure 62 to figure 42 . 26-feb-2010 4 modified figure 1: rhf1401 block diagram . added details for tdr and changed values for tpd in table 5: timing characteristics . modified figure 11: timing diagram . changed values for vrefp in ta b l e 4 . changed vin operating conditions in ta b l e 4 , figure 42 and figure 55 . changed values for dnl in ta b l e 9 . 13-sep-2010 5 modified figure 1 on page 7 and figure 9 on page 11 . added note 2. on page 13 . modified c in typ value in table 6: analog inputs as per figure 3 . modified figure 11: timing diagram . replaced figure 18 . added table 12: output codes for dfsb = 1 . modified figure 53: 2 vpp differential input . 29-jul-2011 6 added note: on page 31 and in the "pin connections" diagram on the cover page.
rhf1401 revision history doc id 13317 rev 8 41/42 06-apr-2012 7 added table 1: device summary on cover page. updated curves in section 2.3: electrical characteristics (after 300 krad) . modified section 3.1: optimizing the power consumption . modified section 3.2: driving the analog input . modified section 3.3.1: internal voltage reference . modified section 3.3.2: exter nal voltage reference . modified section 3.6: pcb layout precautions . 24-oct-2012 8 updated ta bl e 1 modified figure 1: rhf1401 block diagram modified figure 4: output buffers modified ta b l e 4 , ta b l e 7 , and ta bl e 8 modified section 2.4: results for differential input modified section 2.5: results for single ended input added comments and changed layout of section 3.2: driving the analog input . modified ta b l e 1 2 modified figure 55 added ta b l e 1 3 added comments to section 3.3: reference connections modified section 3.5.1: digital inputs table 17. document revision history (continued) date revision changes
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